This disclosure relates generally to semiconductor manufacturing and more particularly to a method for manufacturing a semiconductor device with reduced floating body effect.
Silicon-On-Insulator (SOI) is the substrate choice in future generation integrated circuits. SOI typically consists of a silicon substrate with an insulator layer buried in it, with semiconductor devices built into a layer of silicon on top of the insulator layer. SOI provides improved performance due to reduced parasitic capacitances and enhanced isolation of devices.
However, the use of SOI can result in the floating body effect, where charge exists in the transistor body for extended periods of time, causing threshold voltages to vary. Several methods exist for reducing the floating body effect, including a Ge source/drain implant, an Ar implant, an In halo implant, and the use of a bipolar embedded source structure (BESS). However, the implanting of Ge, Ar, or In increases the junction leakage in the device, and the BESS is not a self aligning process.
Adopting a narrow bandgap material, such as SiGe alloy, is useful to reduce charges existing in the transistor body. With smaller bandgap due to the offset of the valence band, holes can flow out the transistor body more easily. SiGe source/drain is a well-known structure to provide uniaxial compressive stress to improve P-FET performance, as disclosed by INTEL. However, it is detrimental to the N-FET. Therefore, it is important to keep SiGe source/drain away from the channel surface of the N-FET.
Accordingly, it would be desirable to provide a method of manufacturing a semiconductor device with reduced floating body effect absent the disadvantages discussed above.